Abstract
Digital Matched Filter (DMF) is the key component of fast Pseudo Noise (PN) Code synchronization in Direct Spread- Spectrum Systems (DSSS), and its realization is a crucial technology of digital DSSP receiver. For long PN code DMF needs a mass of hardware resource, recursive delay chain, folded DMF and Time-Division Multiplexing are used to optimize FPGA realization of DMF to reduce the consumption of FPGA resource, which would reduce the cubage and cost of the receivers'.