Abstract
This paper proposes a new processor architecture optimized for execution of sequential instruction streams. Thearchitecture, called Grid Alu Processor (GAP), comprises an in-order superscalar pipeline front-end enhanced by aconfiguration unit able to dynamically issue dependent andindependent standard machine instructions simultaneously to the Arithmetic Logic Uunits (ALUs) organized in atwo-dimensional array. In contrast to well-known coarse-grained reconfigurable architectures no special synthesis tools are required and no configuration overhead occurs. Simulations of the GAP show a maximum Instructions Per Cycle (IPC) speedup of about 2.56 compared to the results of an equivalently configured SimpleScalar processor simulator.