Abstract
The growing diffusion of embedded systems in the most diverse application domains contributes to the increasing complexity of their development. Hardware/Software Co-Design methodologies are usually employed to tackle the complexity deriving from even more stringent functional and non-functional requirements. This kind of methodology envisages a unified and technology-independent system model to perform several verification and validation steps at the early stages of the design. This model should be rigorously examined to reduce the likelihood of faulty behaviors during the implementation stages. In this research, we investigate the integration of formal verification and validation in a Hardware/Software Co-Design methodology. We introduce a novel model-driven co-design flow, called V&V-based Hardware/Software Co-Design, that leverages several model-to-model transformations from a UML/MARTE model to different formalisms. Each formalism is exploited to verify and validate a distinct aspect of the system. At the current stage, we are testing the proposed methodology through a case study characterized by a component-based architecture and a reactive behavior. Specifically, we realized the first two stages, namely Co-Specification and Co-V&V. The former is intended for system modeling, whereas the Co-V&V is for functional verification and timing validation. The Co-V&V indicates that our approach is particularly effective in discovering design flaws located in the communication protocol as well as those arising from the internal behavior of components.