Compact SPICE Models of the Standard Layout Fragments in LSI Interconnections

K.O. Petrosyants; N.I. Ryabov; E.I. Batarueva

doi:10.1109/EWDTS.2018.8524730

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2018 IEEE East-West Design & Test Symposium (EWDTS)

Compact SPICE Models of the Standard Layout Fragments in LSI Interconnections

Year: 2018, Pages: 1-5

DOI Bookmark: 10.1109/EWDTS.2018.8524730

Authors

K.O. Petrosyants, (Moscow Institute of Electronics and Mathematics), National Research University Higher School of Economics
N.I. Ryabov, (Moscow Institute of Electronics and Mathematics), National Research University Higher School of Economics
E.I. Batarueva, (Moscow Institute of Electronics and Mathematics), National Research University Higher School of Economics

Compact SPICE Models of the Standard Layout Fragments in LSI Interconnections

Authors

Abstract