Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA

M. Renovell; P. Faure; P. Prinetto; Y. Zorian

doi:10.1109/DELTA.2002.994634

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Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002

Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA

Year: 2002, Pages: 297

DOI Bookmark: 10.1109/DELTA.2002.994634

Authors

M. Renovell, LIRMM - UM2
P. Faure, LIRMM - UM2
P. Prinetto, Polytecnico de Torino
Y. Zorian, Logic Vision Inc.

Abstract

This paper proposes a new and original solution to test the uni-dimensionnal interconnect architecture of a RAM based FPGA by exploring the specific properties of these blocks. The method to find a reduced set of configurations is proposed and the sequence of test vectors required for each configuration is given.

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