Abstract
When an over-the-cell routing layer is available for a VLSI standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. Three physical models are presented to utilize the area over the cells for routing in standard cell designs. Also presented are efficient algorithms to choose and to route a planar subset of nets over the cells so that the resulting channel density is reduced as much as possible. For each of the physical models, it is shown how to arrange inter-cell routing, over-the-cell routing and power/ground buses to achieve valid routing solutions. Each algorithm exploits the particular arrangement in the corresponding physical model and produces provably good results in polynomial time. The saving in routing area achieved by these algorithms is up to 21 %.