Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check

A heuristic design-for-checkability method based on observation point insertion in the Circuit Under Check (CUC) is proposed to increase the error detection ability of Concurrent Checkers (CC). In particular, at least 99% of error detection is obtained for parity checkers and almost all ISCAS'85 benchmark circuits by inserting 2-5 groups of observation points compacted by parity trees.