Automated SEU fault emulation using partial FPGA reconfiguration

Uros Legat; Anton Biasizzo; Franc Novak

doi:10.1109/DDECS.2010.5491825

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

Automated SEU fault emulation using partial FPGA reconfiguration

Year: 2010, Pages: 24-27

DOI Bookmark: 10.1109/DDECS.2010.5491825

Authors

Uros Legat, Computer Systems Department, Jozef Stefan Institute, Ljubljana, Slovenia
Anton Biasizzo, Computer Systems Department, Jozef Stefan Institute, Ljubljana, Slovenia
Franc Novak, Computer Systems Department, Jozef Stefan Institute, Ljubljana, Slovenia

Abstract

FPGAs are subjected to SEU faults. Fault emulation methods are used to verify the behavior of the system in the presence of fault. In this paper an automated fault emulation approach is presented. An original, fully automated extraction of SEU fault sources is introduced and the injection procedure for various types of faults in FPGA configuration and user memory is explained. Faults are injected during run-time using an embedded microprocessor. Only the resources affected by the faults are reconfigured. A prototype fault injection tool was developed and the approach is demonstrated on two different FPGA applications, micro processor BIST, and AES BIST.

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Automated SEU fault emulation using partial FPGA reconfiguration

Authors

Abstract

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