Low-area boundary BIST architecture for mesh-like network-on-chip

Current paper proposes a Built-In Self-Test (BIST) architecture for targeting the routing infrastructure of mesh-like NoCs from their boundaries. The architecture contains a counter and a Finite State Machine (FSM) implementing the test configurations. Test data is generated and test responses compacted by a dedicated hardware structure requiring very little silicon area. The advantages of this new boundary BIST concept with respect to existing methods is that costly data wrappers in the NoC network are unnecessary, and thus, area and performance penalties are avoided. We have also improved previously developed test configurations. Experiments show that up to two orders of magnitude gains in the speed of testing are achieved using the new method for large NoCs.