Abstract
The paper describes a modified Smart BIST methodology that provides test data volume compression. The test equipment is easily applicable because it is based on the standard scan methodology. The method is based on continuous LFSR reseeding decompression that is used in such a way that it enables lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. We propose a modified LFSR with state skipping for the pattern decompression that does not require a phase shifter and saves hardware. A pattern encoding algorithm minimizing the number of clock cycles of the decompressor needed for decoding test patterns is also proposed. The parameters can be tuned in such a way that the method provides similar data magnitude reduction and decompressor hardware overhead as other test compression methods but it substantially reduces test time, number of tester channels and hardware overhead. Experimental results of benchmark circuit testing show that the modified Smart BIST methodology provides unreduced test coverage, low hardware overhead and short test sequences.