2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Evaluating the Resilience of Parallel Applications
DOI Bookmark: 10.1109/DFT.2018.8602987
Authors
Mark Wilkening, CS Department, Harvard University, Cambridge, MA, USAFritz Previlon, ECE Department, Northeastern University, Boston, MA, USA
David R. Kaeli, ECE Department, Northeastern University, Boston, MA, USA
Sudhanva Gurumurthi, AMD Research, Advanced Micro Devices, Inc., Austin, TX, USA
Steven Raasch, AMD Research, Advanced Micro Devices, Inc., Boxborough, MA, USA
Vilas Sridharan, RAS Architecture, Advanced Micro Devices, Inc., Boxborough, MA, USA