Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAs

Zhen Gao; Jiajun Xiao; Pedro Reviriego

doi:10.1109/DFT52944.2021.9568339

Previous
Next
Table of Contents
Related Articles

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAs

Year: 2021, Pages: 1-4

DOI Bookmark: 10.1109/DFT52944.2021.9568339

Authors

Zhen Gao, Tianjin University,School of Electrical and Information Engineering,Tianjin,China
Jiajun Xiao, Tianjin University,School of Electrical and Information Engineering,Tianjin,China
Pedro Reviriego, Universidad Carlos III de Madrid,Departamento de Ingeniería Telemática,Madrid,Spain

Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAs

Authors

Abstract