A yield study of VLSI adders

Zhan Chen; I. Koren

doi:10.1109/DFTVS.1994.630035

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

A yield study of VLSI adders

Year: 1994, Pages: 239,240,241,242,243,244,245

DOI Bookmark: 10.1109/DFTVS.1994.630035

Authors

Zhan Chen, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren

Abstract

Several 64-bit adders have been designed and their expected yield has been estimated. Our results show that the yield of VLSI adders can be improved by modifying the layout of the original design and/or by choosing a different layout and circuit structure. In certain situations, these approaches can improve the yield by 10% to 17%.

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A yield study of VLSI adders

Authors

Abstract

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