Layout automation of CMOS analog building blocks with CADENCE

D. Dzahini; F. Gaffiot; B. Boutherin; M. Le Helley

doi:10.1109/EASIC.1990.207915

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EURO ASIC `90

Layout automation of CMOS analog building blocks with CADENCE

Year: 1990, Pages: 86,87,88

DOI Bookmark: 10.1109/EASIC.1990.207915

Authors

D. Dzahini, LEAME, CNRS, Ecole Centrale de Lyon, Ecully, France
F. Gaffiot, LEAME, CNRS, Ecole Centrale de Lyon, Ecully, France
B. Boutherin, LEAME, CNRS, Ecole Centrale de Lyon, Ecully, France
M. Le Helley, LEAME, CNRS, Ecole Centrale de Lyon, Ecully, France

Layout automation of CMOS analog building blocks with CADENCE

Authors

Abstract