Functional verification for retiming and rebuffering optimization

A.P. Kostelijk; A. van der Werf

doi:10.1109/EDAC.1993.386493

1993 European Conference on Design Automation with the European Event in ASIC Design

Functional verification for retiming and rebuffering optimization

Year: 1993, Pages: 99,100,101,102,103,104

DOI Bookmark: 10.1109/EDAC.1993.386493

Authors

A.P. Kostelijk, Philips Res. Lab., Eindhoven, Netherlands
A. van der Werf, Philips Res. Lab., Eindhoven, Netherlands

Abstract

An algorithm which proves or disproves functional consistency of a sequential datapath after a combination of retiming, pipelining and buffering optimizations is presented. The verification algorithm is complete and efficient. It includes verification of external latency constraints. Experiments have confirmed the speed of the implemented algorithm and errors were clearly indicated in industrial designs.<>

Like what you’re reading?

Already a member?

Get this article FREE with a new membership!

Efficient equivalence checking of multi-phase designs using retiming
Proceedings of ICCAD International Conference on Computer Aided Design
Retiming of circuits with single phase transparent latches
1991 IEEE International Conference on Computer Design: VLSI in Computers and Processors
High Speed VLSI Architecture for Squaring Algorithm Using Retiming Approach
2013 Third International Conference on Advances in Computing and Communications (ICACC)
System-Level Retiming and Pipelining
2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Retiming gated-clocks and precharged circuit structures
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
Performance optimization of sequential circuits by eliminating retiming bottlenecks
1992 IEEE/ACM International Conference on Computer-Aided Design
Fixed-phase retiming for low power design
Proceedings of 1996 International Symposium on Low Power Electronics and Design
On the optimization power of retiming and resynthesis transformations
Proceedings of ICCAD International Conference on Computer Aided Design
Multilevel global placement with retiming
Design Automation Conference
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Functional verification for retiming and rebuffering optimization

Authors

Abstract

Related Articles