Abstract
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode. During test application the circuits are subject to an activity higher than in the normal mode: the extra power consumption due to test application can rise severe hazards to circuit reliability. Moreover, it can dramatically shorten the battery life when on-line testing is considered. In this paper we propose a low power BIST architecture inspired by the pre-computation architecture. Experimental results show that our approach can achieve an average power reduction ranging from 31% to 95% without affecting the quality of the test. The new architecture can be easily integrated into an existing design flow and is barely invasive with respect to the original BIST circuit.