European Design Automation Conference with EURO-VHDL
Download PDF

Abstract

The design of high performance ICs requires accurate critical path analysis tools, to verify and design optimal clocking schemes. A theoretical basis is presented, which allows comparison of several path analysis approaches. Finally, an optimal and correct clocking scheme is presented, which does not suffer from the problems of previously published clocking schemes.
Like what you’re reading?
Already a member?
Get this article FREE with a new membership!