Multidimensional loop fusion for low-power

Dmytro Lazorenko

doi:10.1109/EWDTS.2008.5580154

IEEE East-West Design & Test Symposium (EWDTS 2008)

Multidimensional loop fusion for low-power

Year: 2008, Pages: 92-95

DOI Bookmark: 10.1109/EWDTS.2008.5580154

Authors

Dmytro Lazorenko, G.E. Pukhov Institute for Modeling in Energy Engineering, National Academy of Sciences of Ukraine, 15 General Naumov Street, Kyiv, 03164, Ukraine

Abstract

Development of semiconductor technology has led to advent of complex digital systems, such as portable, embedded, SoCs, and FPGA devices. Complexity of modern applications and deep-submicron technologies make low-power design attitude compulsory. The higher the level of abstraction of a design that power optimizations are applied, the higher are potential savings. Memory is known to be extremely power consuming. A new technique of loop fusion to optimize a behavioral description of an application before the hardware/software partitioning is presented in this paper.

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Multidimensional loop fusion for low-power

Authors

Abstract

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