Abstract
A bus-level synchronized computer system is widely Utilized in the field of railway signaling of Japan. It may Be recognized that there is a problem of disadvantage in a manufacturing cost reduction. We intend to integrate a bus-level synchronized FS computer into an LSI chip in expectation of cost reduction and performance enhancement. An economical FS one-chip computer by utilizing system LSI technology is realized. It assures fail-safety by means of new fault diagnosis mechanism depending on an M-sequence code signature. In this paper, these contents and techniques are reported in detail.