Research of local dynamics of the phase-locked loop

Y. A. Gelozhe; P. P. Klimenko; A. V. Maksimov

doi:10.1109/EWDTS.2016.7807698

2016 IEEE East-West Design & Test Symposium (EWDTS)

Research of local dynamics of the phase-locked loop

Year: 2016, Pages: 1-4

DOI Bookmark: 10.1109/EWDTS.2016.7807698

Authors

Y. A. Gelozhe, Engineering and Telecommunication Systems Department, Southern Federal University, Rostov-on-Don, Russia
P. P. Klimenko, Engineering and Telecommunication Systems Department, Southern Federal University, Rostov-on-Don, Russia
A. V. Maksimov, Embedded Systems Department, Southern Federal University, Rostov-on-Don, Russia

Abstract

Measures to reduce the influence of the dead zone of frequency-sensitive phase detector on frequency deviation of the signal generated by the phase-locked loop (PLL) the circuit of which includes the binomial low-pass filter of the fifth order, providing additional ripple suppression of control voltage are defined here. With the help of simulation method of Matlab program it was shown 60°…70° that to reduce the peak frequency deviation it is necessary to ensure the stability margin of the automatic system at phase. Given stability margin from 26° to 80° systematic frequency shift of the generated signal is observed, despite the fact that the system under consideration has astatism of the second order.

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Research of local dynamics of the phase-locked loop

Authors

Abstract

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