Modelling Error Pulses in a CMOS Triple Majority Gate while Exposed to an Ionizing Particle

Yuri V. Katunin; Vladimir Ya. Stenin

doi:10.1109/EWDTS50664.2020.9224697

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2020 IEEE East-West Design & Test Symposium (EWDTS)

Modelling Error Pulses in a CMOS Triple Majority Gate while Exposed to an Ionizing Particle

Year: 2020, Pages: 1-4

DOI Bookmark: 10.1109/EWDTS50664.2020.9224697

Authors

Yuri V. Katunin, Russian Academy of Sciences,Department of Analog and Digital Blocks Design,Moscow,Russia
Vladimir Ya. Stenin, National Research Nuclear University MEPhI (Moscow Engineering Physics Institute),Department of Electronics,Moscow,Russia

Modelling Error Pulses in a CMOS Triple Majority Gate while Exposed to an Ionizing Particle

Authors

Abstract