Hardware/Software Co-design for Machine Learning Accelerators

Hanqiu Chen; Cong Hao

doi:10.1109/FCCM57271.2023.00058

2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

Hardware/Software Co-design for Machine Learning Accelerators

Year: 2023, Pages: 233-235

DOI Bookmark: 10.1109/FCCM57271.2023.00058

Authors

Hanqiu Chen, Georgia Institute of Technology,Electrical and Computer Engineering,Atlanta,USA
Cong Hao, Georgia Institute of Technology,Electrical and Computer Engineering,Atlanta,USA

Abstract

This abstract highlights challenges in machine learning accelerator design and proposes solutions through software/hardware co-design techniques. To optimize single object detection, we introduce Mask-Net, a lightweight network that eliminates redundant computation. To address hardware limitations in Dynamic Graph Neural Networks (DGNNs), we present DGNN-Booster, a graph-agnostic FPGA accelerator. Our designs are open-source, generic, and applicable to real-world scenarios.

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Hardware/Software Co-design for Machine Learning Accelerators

Authors

Abstract

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