A data-parallel programming model for reconfigurable architectures

S.A. Guccione; M.J. Gonzalez

doi:10.1109/FPGA.1993.279476

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Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines

A data-parallel programming model for reconfigurable architectures

Year: 1993, Pages: 79,80,81,82,83,84,85,86,87

DOI Bookmark: 10.1109/FPGA.1993.279476

Authors

S.A. Guccione, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.J. Gonzalez, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

A data-parallel programming model for reconfigurable architectures

Authors

Abstract