A Compensated Technique for 2.5-GHz Ring-Oscillator-Based PLL used in Wireless Transmission

Similar Articles

• A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology
  2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
• The Design and Simulation of a VCO in CMOS Digital PLL
  Intelligent Computation Technology and Automation, International Conference on
• CAD tool for PLL Design
  14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
• A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
• A 104-GHz phase-locked loop using a VCO at second pole frequency
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• Efficient PLL Design for Frequency Synthesizers Used in ZigBee Standard Applications
  2018 International Conference on Intelligent Circuits and Systems (ICICS)
• A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fs_RMSJitter, −258.7-dB FOM, and −75.17-dBc Reference Spur
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems