Abstract
MPSoC architectures bring flexibility and performance, but to avoid high power consumption, they still require a careful design. When taking into account variability in advanced CMOS technologies, individual optimization of each chip is necessary. In this paper, we present an approach based on Game Theory to address this issue at run-time in a distributed way, frequencies are dynamically adjusted according to changes in the system, so that power consumption is reduced while application constraints are fulfilled. Software and hardware solutions are proposed for different flexibility/performance trade-offs. Results show a latency of 5ms and an area of 0.014m² for the optimization stage in the hardware implementation. These figures are promising and allow envisaging run-time optimization on large-scale multi-cores.