Hardware implementations of hash function Luffa

Akashi Satoh; Toshihiro Katashita; Takeshi Sugawara; Naofumi Homma; Takafumi Aoki

doi:10.1109/HST.2010.5513102

2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

Hardware implementations of hash function Luffa

Year: 2010, Pages: 130-134

DOI Bookmark: 10.1109/HST.2010.5513102

Authors

Akashi Satoh, National Institute of Advanced Industrial Science and Technology, Research Center for Information Security, 1-18-13, Sotokanda, Chiyoda, Tokyo, 101-0021, Japan
Toshihiro Katashita, National Institute of Advanced Industrial Science and Technology, Research Center for Information Security, 1-18-13, Sotokanda, Chiyoda, Tokyo, 101-0021, Japan
Takeshi Sugawara, Graduate School of Information Sciences, Tohoku University, Sendai, Miyagi, Japan
Naofumi Homma, Graduate School of Information Sciences, Tohoku University, Sendai, Miyagi, Japan
Takafumi Aoki, Graduate School of Information Sciences, Tohoku University, Sendai, Miyagi, Japan

Abstract

This paper presents hardware architectures for the hash algorithm Luffa, which is a candidate for the next-generation hash standard SHA-3. The architectures were implemented by using a 90-nm CMOS standard cell library. A high throughput of 35 Gbps for a high-speed architecture and a gate count of 14.7 kgate for a compact architecture were obtained. In comparison with Keccak, other SHA-3 candidate in the sponge function category, as well as with the current hash standard SHA-256, Luffa exhibited the advantage of flexible implementation ranging from high-speed to compact circuits.

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Hardware implementations of hash function Luffa

Authors

Abstract

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