Multi-Ring on-Chip Interconnected Architecture for Spiking Neural Network Hardware Implementations

Junxiu Liu; Dong Jiang; Yuling Luo; Senhui Qiu

doi:10.1109/HPCC-SmartCity-DSS50907.2020.00075

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2020 IEEE 22nd International Conference on High Performance Computing and Communications; IEEE 18th International Conference on Smart City; IEEE 6th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)

Multi-Ring on-Chip Interconnected Architecture for Spiking Neural Network Hardware Implementations

Year: 2020, Pages: 593-598

DOI Bookmark: 10.1109/HPCC-SmartCity-DSS50907.2020.00075

Authors

Junxiu Liu, Guangxi Normal University,School of Electronic Engineering,Guilin,China
Dong Jiang, Guangxi Normal University,School of Electronic Engineering,Guilin,China
Yuling Luo, Guangxi Normal University,School of Electronic Engineering,Guilin,China
Senhui Qiu, Guangxi Normal University,School of Electronic Engineering,Guilin,China

Multi-Ring on-Chip Interconnected Architecture for Spiking Neural Network Hardware Implementations

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Abstract