Abstract
Testing a system for the detection of faults is a big challenge once the circuit has been designed. The system so designed may consist of sub blocks and Modules. The entire system performance depends upon individual modules performance. Hence testing the system includes testing each & every individual module with various test inputs is required. Due to the limitations in Design for testability techniques like scan based techniques and Built in self test (BIST), with lack of at speed testing and large overheads like area and delay. The VLSI circuit designers are attempting to automate the synthesis of RTL circuits from a Behavioral description. This test generation scheme is independent of bit width and as a result it is capable of handling convoluted control/data path circuits. The Design for testability hardware and test generation algorithms is self-contained. As a result they are independent of the data path bit width. It is proposed to analyze the performance of Analog signal circuit by Behavioral synthesis. By using which parameters like response, delay, etc. can be analyzed.