Abstract
This paper proposes a digital design methodology aiming at introducing certain degrees of reliability in case of hardware failures. Three main differences with respect to the traditional design methodologies for reliability are introduced: first, the peculiarities of the specification language are taken into account by exploiting the features of SystemC to introduce fault detection properties; second, different techniques are considered to determine the best cost/performance trade-off; third, the adoption of the desired reliability properties is carried out transparently to the designer. The three aspects together characterize the proposed approach, presented here through its application to a FIR circuit.