Analytical delay models for VLSI interconnects under ramp input

A.B. Kahng; K. Masuko; S. Muddu

doi:10.1109/ICCAD.1996.568907

Previous
Next
Table of Contents

Computer-Aided Design, International Conference on

Analytical delay models for VLSI interconnects under ramp input

Year: 1996, Pages: 30

DOI Bookmark: 10.1109/ICCAD.1996.568907

Authors

A.B. Kahng, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
K. Masuko, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S. Muddu, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA

Analytical delay models for VLSI interconnects under ramp input

Authors

Abstract