Abstract
The clock distribution network presents one of the most important design challenges in high-performance synchronous VLSI designs. However, automation in clock network synthesis is usually limited to local clock domains for two main reasons. (1) Global clock is too important for designers to take the risk of adopting a fully automated clocking flow. (2) Unlike in other EDA areas (such as synthesis/placement/routing), clock synthesis tools are highly tied to clock network topologies, ground/power planning, clock gating, macro floorplanning, clocking methodologies, etc. It is thus very difficult to implement a set of generic clock synthesis tools for design productivity considerations. That being said, industrial clocking methodologies usually resort to overdesigning because clock synthesis is just too critical to fail.