Abstract
The authors present a novel state assignment technique for synchronous finite state machines (FSMs) that are implemented as single programmable logic arrays (PLAs) using Johnson counters as state memories. The goal is to minimize the number of product terms in the PLAs and thus the overall area of the FSMs. The authors use a three-step approach to achieve this. First, the FSM description is adapted to allow an optimal use of the computer properties; then the counter is embedded by ordering the internal states of the FSM; and finally the states are coded. The product term reductions obtained are, on the average 20% to 30% compared to conventional D-latch-based FSM implementations.<>