A 1.65-V 176-μW 104-dB Continuous Time Delta-Sigma Modulator for Sensor Applications

Xiaofei Chen; Yubin Zhao; Yuxiang Tang; Shuangxi Lin

doi:10.1109/ICEEE2019.2019.00051

2019 6th International Conference on Electrical and Electronics Engineering (ICEEE)

A 1.65-V 176-μW 104-dB Continuous Time Delta-Sigma Modulator for Sensor Applications

Year: 2019, Pages: 230-236

DOI Bookmark: 10.1109/ICEEE2019.2019.00051

Authors

Xiaofei Chen, Huazhong University of Science and Technology
Yubin Zhao, Huazhong University of Science and Technology
Yuxiang Tang, Huazhong University of Science and Technology
Shuangxi Lin, Wuhan Institute of Technology

Abstract

This paper presents a low-noise single-loop third-order single-bit continuous-time (CT) Delta-Sigma modulator for sensor applications. The modulator employs the CIFF-B structure and chopping technique to reduce the power consumption and low-frequency noise. The FIR feedback DAC is adopted to reduce the sensitivity of CT ΔΣ modulators to clock jitter, and the method of moments is used to design the coefficients of loop filter. The chopping frequency is also designed carefully to avoid the noise aliasing effect, and modulator coefficients and circuit implementation have been optimized for low power. The modulator, implemented in a 150nm CMOS technology with a core area of 0.48mm², achieves a 107dB peak SNR and a 104dB peak SNDR over a 1kHz signal bandwidth. The power consumption is 176μW at 1.65V supply voltage.

Like what you’re reading?

Already a member?

Get this article FREE with a new membership!

Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR
Electronic Design, Test and Applications, IEEE International Workshop on
Green Bandpass Sigma Delta Modulator with Capacitive Feedforward Summation and Series-Peaking LNA Chip Design for Communication System Application
2014 IEEE International Conference on Internet of Things(iThings), and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing(CPSCom)
A Low Power Multi-channel Input Delta-Sigma ADC without Reset
2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)
A 15 Bit 95 dB Low Power Discrete Time Sigma Delta Modulator
Communication Systems, International Conference on
A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications
VLSI Design, International Conference on
Multi-loop sigma-delta quantization: spectral analysis
ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing
A 2-MHz BW 82-dB DR Continuous-Time Delta–Sigma Modulator With a Capacitor-Based Voltage DAC for ELD Compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Continuous-Time MASH 1-1-1 Delta–Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A 1.65-V 176-μW 104-dB Continuous Time Delta-Sigma Modulator for Sensor Applications

Authors

Abstract

Related Articles