Abstract
Multi-FPGA with the cascade structure is widely used, which urgently needs the low power loading fuction in the long term working stage. For the same size configuration file, choosing different configuration modes, the configuration circuit design and configuration time could be very different. To analyse the effects for the Multi-FPGA structures, the typical model is researched respectively on master serial (MS), slave serial (SS), slave parallel (SP), active parallel (AP), master parallel (MP), fast SPI, standard SPI and JTAG configuration. And it is demonstrated on the management design of multi-FPGA cascade loading, including factors to be considered, when choosing a configuration mode with overall setup, speed, cost, program upgrade complexity, and applications. Among them, to lower the power, even though the JTAG cascade mode has fast loading speed, the product still needs to be equipped with peripheral devices, such as emulators when upgrading, which is inconvenient to use; the MCU loading mode has slow loading speed, complex overall settings and low cost, and requires a remote computer and network to backup the upgrading; the flash loading mode with fast loading speed, complex overall setting and high cost, supports both remote and local upgrade modes. With all these setting to get the lowest power consumption, the specified type for the MultiFPGA simulation with the cascade structure can only take 2.7 s to load, with the33 MHz clock.