A Parameter to Measure the Efficiency of FPGA Based Logic Synthesis Tools

In FPGA-based designs, the number of Logic Cells (LCs) needed is an important criterion to judge whether a design is good or not. However, the total number of LCs required to implement a circuit differs vastly from tool to tool. Normally, vendor software uses more LCs than the theoretical maximum needed by functional decomposition to implement a circuit. Academic software uses less number of LCs. So far, we are not aware of any technique that would give a quantitative measure to judge the comparable silicon area efficiency of a logic synthesis tool. This paper presents a technique to calculate the minmax number of logic cells (Q) needed to implement a logic circuit. It is proved that the total number of LCs needed to implement a circuit is less than or equal to Q.