Abstract
Multiple-reference-frame, quarter-pixel accuracy, and variable-block-size motion estimation (VBSME) employed in H.264/AVC is one of the major contributors to its outstanding compression efficiency and video quality. However, due to its high computational complexity, VBSME needs acceleration for real-time application. We propose a high throughput hardware architecture for H.264/AVC fractional motion estimation (FME). The proposed architecture consists of three parallel processing engines. In addition, we propose a resource sharing method which leads to 50% hardware saving in the computation sum of absolute transformed difference (SATD). Synthesized into a TSMC 130 nm CMOS cell library, our design takes 311.7K gates at 154 MHz and can encode 1080 pHD video at 30 frames per second (fps). Compared to previous works, the proposed design runs at much lower frequency for the same resolution and frame rate.