A symbolic RTL synthesis for LUT-based FPGAs

Stanislaw Deniziak; Mariusz Wisniewski

doi:10.1109/DDECS.2009.5012107

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2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

A symbolic RTL synthesis for LUT-based FPGAs

Year: 2009, Pages: 102-107

DOI Bookmark: 10.1109/DDECS.2009.5012107

Authors

Stanislaw Deniziak, Dept. of Computer Engineering, Cracow University of Technology, Warszawska 24, 31-155, Poland
Mariusz Wisniewski, Dept of Computer Science, Kielce University of Technology, Al. 1000-lecia PP 7, 25-314, Poland

A symbolic RTL synthesis for LUT-based FPGAs

Authors

Abstract