A realistic fault model for flash memories

Yea-Ling Horng; Jing-Reng Huang; Tsin-Yuan Chang

doi:10.1109/ATS.2000.893637

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Proceedings of the Ninth Asian Test Symposium

A realistic fault model for flash memories

Year: 2000, Pages: 274

DOI Bookmark: 10.1109/ATS.2000.893637

Authors

Yea-Ling Horng, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Jing-Reng Huang, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Tsin-Yuan Chang, Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Abstract

To explore all faulty behavior on NAND-type flash memory is impractical, and the defects in the SPICE model level are considered. In this paper, two SPICE models of the flash cell are developed and used for circuit-level faulty behavior simulation. The faulty behaviors can be classified to six types and applied for the fault modeling or testing of NAND-type flash memory.

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