Abstract
This paper presents an approximate three-operand adder, highlighting its advantages in terms of speed, power consumption, and area utilization compared to conventional adders. an approximate three-operand adder is designed using 45 nm technology. The adders are implemented for 16-bit, 32-bit, and 64-bit operands. A comprehensive comparison of these adders in terms of area, power, and delay is presented. Accuracy metrics, including error distance, error rate, MED, and NED are also computed to evaluate the performance of the proposed adder. The results show that the proposed approximate adder is 1.1 times faster than the existing adder, consumes 18% less power, and utilizes 12% less core area. These improvements make it an attractive choice for practical applications. To further demonstrate its efficiency, an image-processing application is included in the paper. The evaluation metrics confirm the effectiveness of the proposed design, making it a promising option for various error-resilient applications like multimedia and image-processing.