Abstract
Neural network architectures are increasingly pop-ular for their ability to perform fast and efficient compu-tations, leveraging inherent parallelism for quicker operation than conventional sequential methods. This paper presents a novel reconfigurable neural network architecture implemented with computationally less intensive hardware, along with a hardware accelerator-based design of a feed-forward neural network. The primary aim of this work is to optimize power and area utilization metrics using an approximate computing paradigm and a control unit that synchronizes the forward and backward passes. Moreover, in this paper, we introduce a compact and scalable hardware design approach for neural networks, validated through simulations and implementations on Xilinx Zynq and Zynq UltraScale+ MPSoC FPGA boards. Our architecture significantly reduces area overhead by 2.58 %, enhances power efficiency with an average power consumption of 110.67 mW, and achieves a 4.68-fold increase in throughput compared to software implementations. This improvement, while maintaining an average accuracy of around 91 % across different architectures, is due to the use of reconfigurable features and Padé-based optimization techniques.