Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm

S. Ramsundar; Ahmad Al-Yamani; Dhiraj K. Pradhan

doi:10.1109/ISQED.2007.55

2007 IEEE International Symposium on Quality of Electronic Design

Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm

Year: 2007, Pages: 807-813

DOI Bookmark: 10.1109/ISQED.2007.55

Authors

S. Ramsundar, Indian Institute of Technology, India
Ahmad Al-Yamani, KFUPM, Saudi Arabia
Dhiraj K. Pradhan, University of Bristol, United Kingdom

Abstract

Lithography based IC fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques.

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Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm

Authors

Abstract

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