Join Us
Sign In
My Subscriptions
Magazines
Journals
Video Library
Conference Proceedings
Individual CSDL Subscriptions
Institutional CSDL Subscriptions
Resources
Career Center
Tech News
Resource Center
Press Room
Advertising
Librarian Resources
IEEE.org
Help
About Us
Career Center
Cart
Create Account
Sign In
Toggle navigation
My Subscriptions
Browse Content
Resources
All
Previous
Next
Table of Contents
Related Articles
Home
Proceedings
ISVLSI
ISVLSI 2017
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem
Year: 2017, Pages: 116-121
DOI Bookmark:
10.1109/ISVLSI.2017.29
Authors
Zarrin Tasnim Sworna
Mubin Ul Haque
Hafiz Md. Hasan Babu
Lafifa Jamal
Ashis Kumer Biswas
Download PDF
SHARE ARTICLE
Generate Citation
Abstract
