A Fully Digital Foreground Calibration Technique of A Flash ADC

Shatadal Chatterjee; Maryaradhiya Daimari; Sounak Roy

doi:10.1109/ISVLSI51109.2021.00012

2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

A Fully Digital Foreground Calibration Technique of A Flash ADC

Year: 2021, Pages: 1-6

DOI Bookmark: 10.1109/ISVLSI51109.2021.00012

Authors

Shatadal Chatterjee, Indian Institute of Information Technology,Dept. of Electronics And Communication Engineering,Guwahati,India,781015
Maryaradhiya Daimari, Indian Institute of Information Technology,Dept. of Electronics And Communication Engineering,Guwahati,India,781015
Sounak Roy, Indian Institute of Information Technology,Dept. of Electronics And Communication Engineering,Guwahati,India,781015

Abstract

This paper presents a digital domain foreground calibration algorithm for flash analog-to-digital converters (ADC). In deep sub-micron technologies, for low voltage and low power applications, random mismatch appearing in comparator circuits induce large offset voltages. The linearity of a flash ADC gets adversely affected by the offset voltages. In the proposed method, a lookup table (LUT) based offset calibration technique has been introduced to nullify the effect of comparator offset voltages to improve the linearity of the flash ADC. Behavioural simulation result of a 6 bit flash ADC shows that after calibration SNDR gets improved from 28.01 dB to 33.23 dB.

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A Fully Digital Foreground Calibration Technique of A Flash ADC

Authors

Abstract

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