PACE: MLP-Based Fast and Accurate Per-Cycle Chip Power Modelling

Cem Benar; George Phan; Sylvia Chan; Zongfang Lin; Yat Fai Lam; Robert Chu

doi:10.1109/ISVLSI61997.2024.00132

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2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

PACE: MLP-Based Fast and Accurate Per-Cycle Chip Power Modelling

Year: 2024, Pages: 689-693

DOI Bookmark: 10.1109/ISVLSI61997.2024.00132

Authors

Cem Benar, New Jersey Institute of Technology,Department of Electrical and Computer Engineering,Newark,NJ,USA
George Phan, Futurewei Technologies,Santa Clara,CA,USA
Sylvia Chan, Futurewei Technologies,Santa Clara,CA,USA
Zongfang Lin, Futurewei Technologies,Santa Clara,CA,USA
Yat Fai Lam, Futurewei Technologies,Santa Clara,CA,USA
Robert Chu, Futurewei Technologies,Santa Clara,CA,USA

PACE: MLP-Based Fast and Accurate Per-Cycle Chip Power Modelling

Authors

Abstract