A Memory Aware High Level Synthesis Tool

Gwenol? Corre; Eric Senn; Nathalie Julien; Eric Martin

doi:10.1109/ISVLSI.2004.1339557

IEEE Computer Society Annual Symposium on VLSI

A Memory Aware High Level Synthesis Tool

Year: 2004, Pages: 279

DOI Bookmark: 10.1109/ISVLSI.2004.1339557

Authors

Gwenol? Corre, University of South-Brittany
Eric Senn, University of South-Brittany
Nathalie Julien, University of South-Brittany
Eric Martin, University of South-Brittany

Abstract

We introduce a new approach to take into account the memory architecture and the memory mapping in High-Level Synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

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