Abstract
In this paper we propose the novel DONUT (Double Node Upset Tolerant) latch, a soft error tolerant latch for SNUs (Single Node Upsets) and DNUs (Double Node Upsets). The latch comprises four DICE cells in a multi-interlocked scheme where each DICE cell is always guaranteed two stable nodes, rendering the DONUT latch resilient to SNUs and DNUs. The proposed latch design merges efficiently the four DICE cells saving 25% of the required transistors. Regarding the power dissipation and propagation delay, simulation results showed that the DONUT latch performs better compared to other BISER-based latches that are SNU or DNU tolerant.