Abstract
Most published ATPG methods cannot handle three-state primitives, generate too large test sets, or require excessive CPU time. An efficient ATPG system was introduced in [Proc. of 13th VLSI Test Symposium][Proc. of 12th VLSI Symposium], which can handle non-Boolean primitives, generates compact test sets, within affordable CPU time. In this paper, the system is extended to handle pulled and wired buses, in addition to pure three-state buses. These bus types are widely used in industrial circuits. Furthermore five techniques for test generation are proposed to acclerate (compact) ATPG. Experimental results demonstrate that these new techniques are useful: ATPG times for compact test set generation are decreased up to 50% compared to [Proc. of 13th VLSI Test Symposium], and fault efficiencies above 99% can be obtained for even the largest cirucits.