OPTIMAL ANALOG TRIM TECHNIQUES FOR IMPROVING THE LINEARITY OF PIPELINE ADCs

Turker Kuyel; Frank Tsay

doi:10.1109/TEST.2000.894226

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)

OPTIMAL ANALOG TRIM TECHNIQUES FOR IMPROVING THE LINEARITY OF PIPELINE ADCs

Year: 2000, Pages: 367

DOI Bookmark: 10.1109/TEST.2000.894226

Authors

Turker Kuyel, Texas Instruments Inc.
Frank Tsay, Texas Instruments Inc.

Abstract

AThis paper investigates the issue of capacitor trimming to improve the linearity of pipeline ADCs that use switched capacitor sub-DACs. Capacitor mismatches create linearity errors, which deteriorate THD, SINAD and SFDR performance of the ADC in communication applications. Measurement of capacitor mismatches and generation of trim capacitor values are discussed. The derivations are for 2-bit-per-stage pipeline ADC architectures and they can easily be extended for any pipelined ADC. Finally, the effectiveness of the overall capacitor trimming process in terms of cost and performance is analyzed for a 12bit 40MSPS ADC.

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OPTIMAL ANALOG TRIM TECHNIQUES FOR IMPROVING THE LINEARITY OF PIPELINE ADCs

Authors

Abstract

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