Abstract
Accurate detection and fast resolution of device measurement is one of the most intriguing test challenges now and in the foreseeable future. This is especially true for those devices with Input Output (IO) speeds and electrical characteristics, which exceed the Automatic Test Equipment (ATE) Edge Placement Accuracy (EPa) and/or Overall Tester Accuracy (OTA). The Tester Derating Factor (TDF) Methodology described in this paper is an evolving Solutions Matrix being used by the Intel Chipset Engineering Group to leverage this challenge into a competitive advantage. This paper describes how the TDF matrix can help engineers take full advantage of existing equipment, including testing devices beyond the vendor specified published EPA/OTA, and suggests ways for the ATE vendors to partner with users to enable this capability on existing / future testers.