IEEE 1500 utilization in SOC design and test

Integrating numerous IP cores into a SoC design is a complex activity from the design-for-testability point of view. Also, accessing and exercising test and diagnosis patterns on each IP core during the manufacturing phases is a major challenge. Designing the IEEE 1500 standard into the IP core and leveraging it during the DFT integration and manufacturing phases drastically simplify these challenges. This paper demonstrates the use of IEEE 1500 in embedded memory IP cores, and describes how it can be leveraged in a SoC during its design and manufacturing phases.